Ternary "flip-flap-flop" We know that the binary memory element called the "flip-flop" is the most important element of modern computers. It is well known that the basis of the classical binary "flip-flop" is logical circuit consisting of the two logical elements 1 and 2 of the kind OR-NOT (Fig. 1-a), which are connected by the back logical connections.
Let's consider now the logical circuit consisting of the three logical elements 1, 2, 3 of the kind OR-NOT (Fig. 1-b). Let's assume that the logical elements 2 and 3 are neighboring to the logical element 1, the logical elements 3 and 1 are neighboring to the logical element 2, and the logical elements 1 and 2 are neighboring to the logical element 3. Each logical element OR-NOT is connected to its neighboring logical elements by the back logical connections. This causes three stable states of the logical circuit in Fig.1-b. Really, let's assume that we have the logical 1 on the input C of the logical element 2. This logical 1 enters the inputs of the neighboring logical elements 1 and 3 and supports the logical 0 on their outputs A and B. These logical 0's enter the inputs of the logical element 2 and support the logical 1 on its output C. Hence this state of the circuit in Fig.1-b is the first stable state. This stable state corresponds to the code combination 0 1 0 on the outputs A, C, B. One may show that the circuit has still two stable states corresponding to the code combinations 1 0 0 and 0 0 1 on the outputs A, C, B. We can use the above-mentioned stable states of the circuit in Fig.1-b for the binary coding of the ternary numerals according to the following table: 0 = 0 1 0 If we eliminate the middle output C we will get the binary outputs A and B, which correspond to the binary coding of the ternary variables according to the following table: 0 = 0 0 Hence the logical circuit in Fig.1-b may be considered as the ternary-binary memory element called the "flip-flap-flop". Let's consider the functioning of the "flip-flop-flap" in Fig.1-b. It has three stable states`1, 0 and 1. Let's suppose that the "flip-flop-flap" in Fig.1-b is in the state Q = 0. This means that the output C = 1, other outputs A = B = 0. If we need to set the "flip-flap-flop" into the state Q = 1 (0 0 1) we should send to the "flip-flap-flop" inputs S, I, R the following code signals S = 1, I = 1, R = 0. The signals S = 1 and I = 1 cause the appearance of the logical 0's on the outputs A and C. These logical 0's enter the inputs of the logical element 3 and together with the logical signal R = 0 cause the appearance of the logical 1 on the output B. By analogy one may show that the signals S = 0, I = 1, R = 1 switches over the "flip-flap-flop" in Fig. 1-b into the state`1 (100). Let's discuss the result obtained above. Now we know how one may design the ternary memory element called the "flip-flap-flop". And comparing the "flip-flop" with the "flip-flap-flop" in Fig.1 we can see that the "flip-flap-flop" in Fig. 1-b consists of the same logical elements as the "flip-flop" in Fig. 1-a. And we see that each student of the Computer College can design the ternary register! And each student can realize all mirror-symmetrical structures mentioned above! And we invite the computer students and engineers to attempt to design ternary mirror-symmetrical processors and computers! It seems to us that this problem quite to you under force. And you can approach Donald Knuth's prediction that there will come the day, when the "flip-flap-flop" will change the "flip-flop" and the era of the ternary mirror-symmetrical computers will come! And we wish you successes in this business! |